| QGPN | Description | Technology Family | VCC (V) |
VCC (V) |
Voltage (V) |
F @ Nom Voltage (Mhz) |
ICC @ Nom Voltage (mA) |
tpd @ Nom Voltage (ns) |
Output Drive (IOL/IOH) (mA) |
Input Type | Output Type | Rating | Package Group |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| CD4027B-MIL | CMOS Dual J-K Master-Slave Flip-Flop | CD4000 | 10 | Military | CDIP WAFERSALE |
||||||||
| CD54AC109 | Dual Positive-Edge Triggered J-K Flip-Flops with Set and Reset | AC | Military | CDIP | |||||||||
| CD74HC112 | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset | HC | 2 | 6 | 3.3 5 |
70 | 0.04 | 53 | -6/6 | LVTTL/CMOS | CMOS | Catalog | PDIP SO SOIC TSSOP |
| SN74HC109 | Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset | HC | 2 | 6 | 3.3 5 |
70 | 0.04 | 58 | -4/4 | LVTTL/CMOS | CMOS | Catalog | PDIP SO SOIC |
| CD4027B | CMOS Dual J-K Master-Slave Flip-Flop | CD4000 | 3 | 18 | 10 | 8 | 0.06 | 130 | -1.5/1.5 | TTL | TTL | Military | PDIP SO SOIC TSSOP |
| CD74AC112 | Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset | AC | 1.5 | 5.5 | 3.3 5 |
100 | 0.04 | 11.1 | -24/24 | LVTTL/CMOS | CMOS | Catalog | PDIP SOIC |
| CD54HC73 | High Speed CMOS Logic Dual Negative-Edge Trigger J-K Flip-Flops with Reset | HC | Military | CDIP | |||||||||
| CD54HC109 | High Speed CMOS Logic Dual Positive-Edge Trigger J-K Flip-Flops with Set and Reset | HC | Military | CDIP WAFERSALE |
|||||||||
| CD74ACT109 | Dual Positive-Edge Triggered J-K Flip-Flops with Set and Reset | ACT | 4.5 | 5.5 | 5 | 90 | 0.04 | 11.1 | -24/24 | TTL | CMOS | Catalog | PDIP SOIC |
| SN74ALS109A | Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset | ALS | 4.5 | 5.5 | 5 | 75 | 4 | 15 | -0.4/8 | TTL | TTL | Catalog | PDIP SO SOIC |
| SN74AS109A | Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset | AS | 4.5 | 5.5 | 5 | 35 | 17 | 10.5 | -0.4/8 | TTL | TTL | Catalog | PDIP SO SOIC |
| SN74LS107A | Dual J-K Flip-Flops With Clear | LS | 4.75 | 5.25 | 5 | 35 | 6 | 20 | -0.4/8 | TTL | TTL | Catalog | PDIP SO SOIC |
| SN74LS112A | Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset | LS | 4.75 | 5.25 | 5 | 35 | 6 | 20 | -0.4/8 | TTL | TTL | Catalog | PDIP SO SOIC |
| CD74AC109 | Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset | AC | 1.5 | 5.5 | 3.3 5 |
100 | 0.04 | 11.1 | -24/24 | LVTTL/CMOS | CMOS | Catalog | PDIP SOIC |
| SN74ALS112A | Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset | ALS | 4.5 | 5.5 | 5 | 75 | 4.5 | 18 | -0.4/8 | TTL | TTL | Catalog | PDIP SO SOIC |
| CD74HC109 | High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset | HC | 2 | 6 | 3.3 5 |
70 | 0.04 | 53 | -6/6 | LVTTL/CMOS | CMOS | Catalog | PDIP SOIC |
| CD54HCT112 | High Speed CMOS Logic Dual J-K Flip-Flops with Set and Reset, Negative-Edge Trigger | HCT | Military | CDIP WAFERSALE |
|||||||||
| CD54HC112 | High Speed CMOS Logic Dual J-K Flip-Flops with Set and Reset, Negative-Edge Trigger | HC | Military | CDIP | |||||||||
| CD54ACT112 | Dual Negative Edge Triggered J-K Flip-Flops with Set and Reset | ACT | Military | CDIP | |||||||||
| CD54AC112 | Dual Negative Edge Triggered J-K Flip-Flops with Set and Reset | AC | Military | CDIP | |||||||||
| CD74HCT109 | High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset | HCT | 4.5 | 5.5 | 5 | 25 | 0.04 | 50 | -6/6 | TTL | CMOS | Catalog | PDIP SOIC |
| SN74F112 | Dual J-K Negative-Edge-Triggered Flip-Flop With Clear And Preset | F | 4.5 | 5.5 | 5 | 70 | 19 | 7.5 | -1/20 | TTL | TTL | Catalog | PDIP SO SOIC |
| SN74HC112 | Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset | HC | 2 | 6 | 3.3 5 |
70 | 0.04 | 41 | -4/4 | LVTTL/CMOS | CMOS | Catalog | PDIP SOIC |
| CD54HCT109 | High Speed CMOS Logic Dual Positive-Edge Trigger J-K Flip-Flops with Set and Reset | HCT | Military | CDIP | |||||||||
| CD54HC107 | High Speed CMOS Logic Dual Negative-Edge Trigger J-K Flip-Flops with Reset | HC | Military | CDIP | |||||||||
| CD54ACT109 | Dual Positive-Edge Triggered J-K Flip-Flops with Set and Reset | ACT | Military | CDIP | |||||||||
| SN74S112A | Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset | S | 4.75 | 5.25 | 5 | 50 | 6 | 20 | -1/20 | TTL | TTL | Catalog | PDIP SO SOIC |
| SN74LS109A | Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset | LS | 4.75 | 5.25 | 5 | 35 | 15 | 35 | -0.4/8 | TTL | TTL | Catalog | PDIP SO SOIC |
| CD74HCT107 | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset | HCT | 4.5 | 5.5 | 5 | 25 | 0.04 | 43 | -6/6 | TTL | CMOS | Catalog | PDIP |
| CD74ACT112 | Dual Negative-Edge Triggered J-K Flip-Flops with Set and Reset | ACT | 4.5 | 5.5 | 5 | 90 | 0.04 | 11.1 | -24/24 | TTL | CMOS | Catalog | SOIC |
| CD74HCT112 | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset | HCT | 4.5 | 5.5 | 5 | 25 | 0.04 | 44 | -6/6 | TTL | CMOS | Catalog | PDIP |
| SN74F109 | Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset | F | 4.5 | 5.5 | 5 | 70 | 17 | 9.2 | -1/20 | TTL | TTL | Catalog | PDIP SOIC |
| CD74HCT73 | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset | HCT | 4.5 | 5.5 | 5 | 25 | 0.04 | 48 | -6/6 | TTL | CMOS | Catalog | PDIP SOIC |
| SN54107 | Dual J-K Flip-Flops With Clear | TTL | 4.5 | 5.5 | TTL | TTL | Military | CDIP | |||||
| CD74HC107 | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset | HC | 2 | 6 | 3.3 5 |
70 | 0.04 | 51 | -6/6 | LVTTL/CMOS | CMOS | Catalog | PDIP SOIC |
| CD74HC73 | High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset | HC | 2 | 6 | 3.3 5 |
70 | 0.04 | 40 | -6/6 | LVTTL/CMOS | CMOS | Catalog | PDIP SOIC |
| SN74LS73A | Dual J-K Flip-Flops with Clear | LS | 4.75 | 5.25 | 5 | 35 | 6 | 20 | -0.4/8 | TTL | TTL | Catalog | PDIP SO SOIC |
| SN74LVC112A | Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset | LVC | 2 | 3.6 | 3.3 | 100 | 0.01 | 4.8 | -24/24 | TTL/CMOS | TTL | Catalog | SO SOIC SSOP TSSOP TVSOP |
