| QGPN | Description | Input Frequency (MHz) |
Input Level | Output Frequency (MHz) |
No. of Outputs | Output Level | VCC Out (V) |
Rating | Operating Temperature Range (C) |
Package Group |
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| CDC391 | 1-To-6 Clock Driver With Selectable Polarity | 100 | TTL | 100 | 6 | TTL | 5 | Catalog | SOIC | |
| CDC208 | 5V Dual 1-to-4 clock driver | 60 | TTL | 60 | 8 | CMOS | 5 | Catalog | -40 to 85 | SO SOIC |
| CDCV304 | General Purpose and PCI-X 1:4 Clock Buffer | 200 | LVTTL | 200 | 4 | LVTTL | 2.5 3.3 |
Catalog | -40 to 85 | TSSOP |
| CDC203 | 3.3V 6-Bit Inverter/Clock Driver | 40 | CMOS | 40 | 6 | CMOS | 3.3 | Catalog | SOIC | |
| LMH2190 | Quad Channel 27 MHz Clock Tree Driver with I2C Interface | 27 | SINE / SQUARE | 27 | 4 | SQUARE | 1.8 | Catalog | -20 to 85 | DSBGA |
| CDC2351 | 1-Line to 10-Line Clock Driver With 3-State Outputs | 100 | LVTTL | 100 | 10 | LVTTL | 3.3 | Catalog | 0 to 70 | SOIC SSOP |
| CDC340 | 1-to-8 clock driver with tight AC specification | 80 | TTL | 80 | 8 | TTL | 5 | Catalog | SOIC | |
| CDCLVC1106 | Low Jitter, 1:6 LVCMOS Fan-out Clock Buffer | 250 | LVCMOS | 250 | 6 | LVCMOS | 2.5 3.3 |
Catalog | -40 to 85 | TSSOP |
| CDC3S04 | Quad Sine-Wave Clock Buffer with LDO | 52 | SINE | 52 | 4 | SINE | 1.8 | Catalog | -40 to 85 | DSBGA |
| CDCE18005 | 5/10 Outputs Clock Buffer with Divider | 1500 | LVPECL | 1500 | 5 | LVPECL | 3.3 | Catalog | -40 to 85 | VQFN |
| CDC329A | 1-To-6 Clock Driver With Selectable Polarity | 80 | TTL | 80 | 6 | CMOS | 5 | Catalog | SOIC | |
| CDCV304-EP | Enhanced Product General Purpose and PCI-X 1:4 Clock Buffer | 200 | LVTTL | 200 | 4 | LVTTL | 2.5 3.3 |
HiRel Enhanced Product | -40 to 105 | TSSOP |
| CDCLVC1110 | Low Jitter, 1:10 LVCMOS Fan-out Clock Buffer | 250 | LVCMOS | 250 | 10 | LVCMOS | 2.5 3.3 |
Catalog | -40 to 85 | TSSOP |
| CDCLVC1103 | Low Jitter, 1:3 LVCMOS Fan-out Clock Buffer | 250 | LVCMOS | 250 | 3 | LVCMOS | 2.5 3.3 |
Catalog | -40 to 85 | TSSOP |
| CDC328A | 1-To-6 Clock Driver With Selectable Polarity | 100 | TTL | 100 | 6 | TTL | 5 | Catalog | SOIC SSOP |
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| LMK00804B | Low Skew, 1-to-4 Multiplexed Differential/LVCMOS-to-LVCMOS/TTL Fanout Buffer | 350 | HCSL LVCMOS LVDS LVPECL LVTTL |
350 | 4 | LVCMOS LVTTL |
3.3V, 2.5V, 1.8V, 1.5V | Catalog | -40 to 85 | TSSOP |
| CDC319 | 1-Line to 10-Line Clock Driver with I2C Control Interface | 100 | LVTTL | 100 | 10 | LVTTL TTL |
3.3 | Catalog | 0 to 70 | SSOP |
| CDCLVC1310 | Universal input, 10 output low impedance LVCMOS Buffer | 200 | HCSL LVCMOS LVDS LVPECL SSTL XTAL |
200 | 10 | LVCMOS | 1.5 1.8 2.5 2.8 |
Catalog | -40 to 85 | VQFN |
| CDC1104 | 1 to 4 Configurable Low Frequency Clock Buffer for 3D Displays | 0.00024 | TTL | 0.00012 | 4 | TTL | 3.8 - 5 | Catalog | -40 to 85 | WQFN |
| CDCVF2310-EP | Enhanced Product 2.5-V to 3.3-V High Performance Clock Buffer | 200 | LVTTL | 200 | 10 | LVTTL | 2.5 3.3 |
Military | -55 to 125 | TSSOP |
| CDCLVC1102 | Low Jitter, 1:2 LVCMOS Fan-out Clock Buffer | 250 | LVCMOS | 250 | 2 | LVCMOS | 2.5 3.3 |
Catalog | -40 to 85 | TSSOP |
| CDCLVC1112 | Low Jitter, 1:12 LVCMOS Fan-out Clock Buffer | 250 | LVCMOS | 250 | 12 | LVCMOS | 2.5 3.3 |
Catalog | -40 to 85 | TSSOP |
| CDCVF2310 | High Performance 1:10 Clock Buffer for General Purpose Applications | 200 | LVTTL | 200 | 10 | LVTTL | 3.3 2.5 |
Catalog | -40 to 85 | TSSOP |
| CDC318A | 1-Line To 18-Line Clock Driver With I2C Control Interface | 100 | LVTTL | 100 | 18 | LVTTL TTL |
3.3 | Catalog | SSOP | |
| LMH2191 | Dual Channel 52 MHz Clock Tree Driver | 52 | SINE / SQUARE | 52 | 4 | SQUARE | 1.8 | Catalog | -40 to 85 | DSBGA |
| CDCLVC1108 | Low Jitter, 1:8 LVCMOS Fan-out Clock Buffer | 250 | LVCMOS | 250 | 8 | LVCMOS | 2.5 3.3 |
Catalog | -40 to 85 | TSSOP |
| CDC339 | 1-To-8 (4 Same Frequency, 4 Divide-By-2) Clock Driver With Clear | 80 | TTL | 80 | 8 | TTL | 5 | Catalog | SOIC SSOP |
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| CDC341 | 1-to-8 clock driver with tight AC specification | 80 | TTL | 80 | 8 | TTL | 5 | Catalog | SOIC | |
| LMH2180 | 75 MHz Dual Clock Buffer | 78 | 78 | 2 | 2.5 3.3 5 |
Catalog | -40 to 85 | DSBGA WSON |
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| CDC337 | 1-To-8 (4 Same Frequency, 4 Divide-By-2) Clock Driver With Clear | 80 | TTL | 80 | 8 | CMOS | 5 | Catalog | SOIC | |
| LMK00101 | Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator with Universal Input | 200 | LVCMOS | 200 | 10 | LVCMOS | 3.3V 2.5V 1.8V 1.5V |
Catalog | -40 to 85 | WQFN |
| CDC204 | 5V 6-Bit Inverter / Clock Driver | 80 | CMOS | 80 | 6 | CMOS | 5 | Catalog | SOIC | |
| CDCUN1208LP | Ultra Low Power, 2:8 Fan-out Buffer with Universal Inputs and Outputs | 400 | HCSL | 400 | 8 | HCSL LVDS LVCMOS |
1.8 2.5 3.3 |
Catalog | -40 to 85 | VQFN |
| CDCLVC1104 | Low Jitter, 1:4 LVCMOS Fan-out Clock Buffer | 250 | LVCMOS | 250 | 4 | LVCMOS | 2.5 3.3 |
Catalog | -40 to 85 | TSSOP |
| LMV112 | 40 MHz Dual Clock Buffer | 40 | rail to rail | 40 | 2 | rail to rail | 2.5 3.3 5 |
Catalog | -40 to 85 | WSON |
| LMK00105 | Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator with Universal Input | 200 | LVCMOS | 200 | 5 | LVCMOS | 3.3V 2.5V 1.8V 1.5V |
Catalog | -40 to 85 | WQFN |
| CDC2351-Q1 | Automotive 1-Line to 10-Line Clock Driver With 3-State Outputs | 100 | LVTTL | 100 | 10 | LVTTL | 3.3 | Automotive | -40 to 125 | SSOP |
| CDC3RL02 | Dual-Channel Square/Sine-to-Square Wave Clock Buffer | 52 | SINE / SQUARE | 52 | 2 | SQUARE | 1.8 | Catalog | -40 to 85 | DSBGA |
| CDC351 | 1-Line to 10-Line 3.3V Clock Driver with Tri-State Outputs | 100 | LVTTL | 100 | 10 | LVTTL | 3.3 | Catalog | -40 to 85 0 to 70 |
SOIC SSOP |
| CDCVF310 | High Performance 1:10 Clock Buffer for General Purpose Applications | 200 | LVTTL | 200 | 10 | LVTTL | 2.5 3.3 |
Catalog | -40 to 85 | TSSOP |
| CDC2351-EP | Enhanced Product 1-Line To 10-Line Clock Driver With 3-State Outputs | 100 | LVTTL | 100 | 10 | LVTTL | 3.3 | HiRel Enhanced Product | -55 to 125 | SSOP |
